1. Field of the Invention
This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D-IC) devices and fabrication methods.
2. Discussion of Background Art
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and provides low wiring delay and interconnect energy costs.
There are many techniques to construct 3D stacked integrated circuits or chips including:                Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).        Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D approaches are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,581,349, 8,163,581, 8,378,715, 8,379,458, 8,742,476, 8,642,416, 8,687,399, US patent publications 2013/0083589 and 2013/0241026, and pending U.S. patent application Ser. Nos. 13/274,161, 13/803,437, 13/836,080 and 13/796,930. The contents of the foregoing patents, publications, and applications are incorporated herein by reference.        
An early work on monolithic 3D was presented in U.S. Pat. No. 7,052,941 and follow-on work in related patents includes U.S. Pat. No. 7,470,598. A technique which has been used over the last 20 years to build SOI wafers, called “Smart-Cut” or “Ion-Cut”, was presented in U.S. Pat. No. 7,470,598 as one of the options to perform layer transfer for the formation of a monolithic 3D device. Yet in a related patent disclosure, by the same inventor of U.S. Pat. No. 7,470,598, U.S. application Ser. No. 12/618,542 it states: “In one embodiment of the previous art, exfoliating implant method in which ion-implanting Hydrogen into the wafer surface is known. But this exfoliating implant method can destroy lattice structure of the doped layer 400 by heavy ion-implanting. In this case, to recover the destroyed lattice structure, a long time thermal treatment in very high temperature is required. This long time/high temperature thermal treatment can severely deform the cell devices of the lower region.” Moreover, in U.S. application Ser. No. 12/635,496 by the same inventor is stated: [0034] Among the technologies to form the detaching layer, one of the well known technologies is Hydrogen Exfoliating Implant. This method has a critical disadvantage which can destroy lattice structures of the substrate because it uses high amount of ion implantation. In order to recover the destroyed lattice structures, the substrate should be cured by heat treatment in very high temperature long time. This kind of high temperature heat treatment can damage cell devices in the lower regions.” Furthermore, in U.S. application Ser. No. 13/175,652 it is stated: “Among the technologies to form the detaching layer 207, one technology is called as exfoliating implant in which gas phase ions such as hydrogen is implanted to form the detaching layer, but in this technology, the crystal lattice structure of the multiple doped layers 201, 203, 205 can be damaged. In order to recover the crystal lattice damage, a thermal treatment under very high temperature and long time should be performed, and this can strongly damage the cell devices underneath.” In fact the Inventor had posted a video infomercial on his corporate website, and was up-loaded on YouTube on Jun. 1, 2011, clearly stating in reference to the Smart Cut process: “The wafer bonding and detaching method is well-known SOI or Semiconductor-On-Insulator technology. Compared to conventional bulk semiconductor substrates, SOI has been introduced to increase transistor performance. However, it is not designed for 3D IC either. Let me explain the reasons . . . . The dose of hydrogen is too high and, therefore, semiconductor crystalline lattices are demolished by the hydrogen ion bombardment during the hydrogen ion implantation. Therefore, typically annealing at more than 1,100 Celsius is required for curing the lattice damage after wafer detaching. Such high temperature processing certainly destroys underlying devices and interconnect layers. Without high temperature annealing, the transferred layer should be the same as a highly defective amorphous layer. It seems that there is no way to cure the lattice damage at low temperatures. BeSang has disruptive 3D layer formation technology and it enables formation of defect-free single crystalline semiconductor layer at low temperatures . . . ”
In at least one embodiment presented herein, at least one innovative method and device structure to repair the crystal lattice damage caused by the hydrogen implant is described.
Regardless of the technique used to construct 3D stacked integrated circuits or chips, heat removal is a serious issue for this technology. For example, when a layer of circuits with power density P is stacked atop another layer with power density P, the net generated power density is 2P. Removing the heat produced due to this power density is a significant challenge. In addition, many heat producing regions in 3D stacked integrated circuits or chips have a high thermal resistance to the heat sink, and this makes heat removal even more difficult.
Several solutions have been proposed to tackle this issue of heat removal in 3D stacked integrated circuits and chips. These are described in the following paragraphs.
Publications have suggested passing liquid coolant through multiple device layers of a 3D-IC to remove heat. This is described in “Microchannel Cooled 3D Integrated Systems”, Proc. Intl. Interconnect Technology Conference, 2008 by D. C. Sekar, et al., “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008 by T. Brunschweiler, et al., and “High Performance Heat Sinking for VLSI,” IEEE Electron Device Letters, vol. EDL-2, No. 5, May 1981, by D. B. Tuckerman and R. F. W. Pease.
Thermal vias have been suggested as techniques to transfer heat from stacked device layers to the heat sink. Use of power and ground vias for thermal conduction in 3D-ICs has also been suggested. These techniques are described in “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009 by Hao Yu, Joanna Ho and Lei He.
In addition, thermal limitations during IC fabrication have been a big obstacle on the road to monolithic three-dimensional ICs. The semiconductor and microelectronic processing techniques to form transistors, circuits, and devices, such as, for example, to form some silicon oxides or nitrides, repair damages from processes such as etching and ion-implantation, annealing and activation of ion implanted species, and epitaxial regrow techniques, have processing temperatures (for example, greater than 400° C.) and times at temperature that would damage and harm the underlying metallization and/or device layers and structures. These processes may involve transient (short timescales, such as less than 500 ns short or long wavelength laser pulses) heat exposures to the wafer/substrate being processed, or steady state applications (such as RTA, RTO, spike, flash, CVD, ALD, furnace/oven) of heat and/or heated material, substrates, susceptors or gases that may have processing times of seconds, minutes, or hours.
The passage of thermal energy through an insulating material may occur through three mechanisms; solid conductivity, gaseous conductivity, and radiative (infrared) transmission. The sum of these three components gives the total thermal conductivity of the material. Solid conductivity is an intrinsic property of a specific material. For dense silica, solid conductivity is relatively high (a single-pane window transmits a large amount of thermal energy). However, a substance such as, for example, silica aerogels possess a very small (˜1-10%) fraction of solid silica. Additionally, the solids that are present consist of very small particles linked in a three-dimensional network (with many “dead-ends”). Therefore, thermal transport through the solid portion of silica aerogel occurs through a very tortuous path and is not particularly effective. The space not occupied by solids in an aerogel is normally filled with air (or another gas) unless the material is sealed under vacuum. These gases can also transport thermal energy through the aerogel. The pores of silica aerogel are open and allow the passage of gas (albeit with difficulty) through the material. The final mode of thermal transport through silica aerogels involves infrared radiation. Silica aerogels are also reasonably transparent in the infrared (especially for wavelengths between 3 and 5 microns), whereas carbon aerogels are not. At low temperatures, the radiative component of thermal transport is low, and not a significant problem. At higher temperatures, radiative transport becomes the dominant mode of thermal conduction, and must be dealt with by, for example, incorporation of IR absorbing materials (opacification) in the aerogel matrix, such as carbon black or TiO2. The heat transport may then become by conductive means. Other materials, for example, nanostructured oxides and metals, utilized phonon scattering and reflection mechanisms to provide a thermal barrier.
Aerogels are low-density solid-state materials derived from gel in which the liquid component of the gel has been replaced with gas. Aerogels consist of a complicated cross-linked internal structure of chains of the aerogel constituent molecules with a large number of air/gas/vacuum filled pores that take up most of the volume. Aerogels are commonly synthesized by the Sol-gel process, yet there are many variations of the process. Details are in the referenced documents and in the general industry knowledge base. In general, the Sol-gel process could be described as formation of an oxide network through polycondensation reactions of a molecular precursor in a liquid. The formation of aerogels usually involves two major steps, the formation of a wet gel, and the drying of the wet gel to form an aerogel. Silica aerogels may be prepared from silicon alkoxide precursors. The most common of these are tetramethyl orthosilicate (TMOS, Si (OCH3)4), and tetraethyl orthosilicate (TEOS, Si (OCH2CH3)4). However, many other alkoxides, containing various organic functional groups, can be used to impart different properties to the gel. The initial step in the formation of aerogels is hydrolysis and condensation of alkoxide. As condensation reactions progress the sol will set into a rigid gel. The kinetics of the reaction can be impracticably slow at room temperature, often requiring several days to reach completion. For this reason, acid or base catalysts are added to the formulation. These catalysts speed up the hydrolysis of silicon alkoxide. In acidic environments the oxygen atom in Si—OH or Si—OR is protonated and H—OH or HOR are good leaving groups. The electron density is shifted from the Si atom, making it more accessible for reaction with water. In basic environments nucleophilic attack by OH— occurs on the central Si atom. The amount and type of catalyst used play key roles in the microstructural, physical and optical properties of the final aerogel product. For example aerogels prepared with acid catalysts often show more shrinkage during supercritical drying and are less transparent than base catalyzed aerogels. As reaction progresses, the sol reaches the gel point, that is, the point in time at which the network of linked oxide particles spans the container holding the Sol. At the gel point the Sol becomes an Alcogel. Typical acid or base catalyzed TEOS gels are often classified as “single-step” gels, referring to the “one-pot” nature of this reaction. A more recently developed approach uses pre-polymerized TEOS as the silica source. Pre-polymerized TEOS is prepared by heating an ethanol solution of TEOS with a sub-stoichiometric amount of water and an acid catalyst. This material is redissolved in ethanol and reacted with additional water under basic conditions until gelation occurs. Gels prepared in this way are known as “two-step” acid-base catalyzed gels. These slightly different processing conditions impart subtle, but important changes to the final aerogel product. Single-step base catalyzed aerogels are typically mechanically stronger, but more brittle, than two-step aerogels. While two-step aerogels have a smaller and narrower pore size distribution and are often optically clearer than single-step aerogels. A most important step in the process in making silica aerogels is supercritical drying. This is where the liquid within the gel is removed, leaving only the linked silica network. The process can be performed by venting the ethanol above its critical point (high temperature-very dangerous) or by prior solvent exchange with CO2 followed by supercritical venting (lower temperatures-less dangerous). The alcogels are placed in the autoclave (which has been filled with ethanol). The system is pressurized to at least 750-850 psi with CO2 and cooled to 5-10 degrees C. Liquid CO2 is then flushed through the vessel until all the ethanol has been removed from the vessel and from within the gels. When the gels are ethanol-free the vessel is heated to a temperature above the critical temperature of CO2 (31 degrees C.). As the vessel is heated the pressure of the system rises. CO2 is carefully released to maintain a pressure slightly above the critical pressure of CO2 (1050 psi). The system is held at these conditions for a short time, followed by the slow, controlled release of CO2 to ambient pressure. Under these conditions, the network structure is retained and a gel with large pores is formed. The density of the resulting aerogel will be very low generally somewhere around 0.1 g/cm3. If the gel is dried by evaporation, then the capillary forces will result in shrinkage, the gel network will collapse, and a xerogel is formed.
The methods of preparing silica aerogels are not very successful in the case of carbon aerogels mainly due to the effects of steric hindrance in tetra alkyl ethers. Instead a variant of the Sol-gel process is used. The precursor that is generally used in the synthesis of carbon aerogels is a resorcinol-formaldehyde solution. Polycondensation of resorcinol with formaldehyde in aqueous solutions leads to gels that can be super critically dried with CO2 to form organic aerogels which are called resorcinolformaldehyde (RF) aerogels. Carbon aerogels can be obtained by pyrolysis of resorcinol formaldehyde aerogels in an inert atmosphere. Additives can be included to the base aerogel formulation to reduce the IR radiative properties; these additives can be carbon black, TiO2 and others. (NASA Tech Briefs, November 2009, Nesmith et al.) Many aero & xerogel matrices are damaged during processing such as plasma etching and depositing layers over the matrix. Often it is found that using a post processing treatment will help to heal the damage or at least mitigate the changes that occurred during processing. These post treatments can also be used to make the films hydrophobic. Many papers discuss these treatments for porous Methylsilsesquioxane (MSQ) and aerogel films. (Fruehauf, S., et al., “Hydrophobisation process for porous Low K Dielectric Silica Layers,” Advanced Metallization Conference, Materials Research Society, 287-294 (2010); Gurav, J. L., et al., “Silica Aerogel: Synthesis and Applications,” Journal of Nanomaterials, vol. 2010, id. 409310)
Techniques to remove heat from 3D Integrated Circuits and Chips and protect sensitive metallization and circuit elements from either the heat of processing of the 3D layers or the operationally generated heat from an active circuit, will be beneficial.
Additionally the 3D technology according to some embodiments of the invention may enable some very innovative IC alternatives with reduced development costs, increased yield, and other illustrative benefits.